Generally, a storage medium, such as a NAND-type flash memory, has a characteristic that the number of defective cells increases due to aged deterioration of the storage medium. The increase of the number of defective cells causes the number of code errors to be increased. As a technique for solving such problem, there is proposed a decoder device that decodes data using an error correction code. The error correction code is used for determining a position of a defective bit (i.e. defective cell) in the data to be decoded, which is formed by several bits, and for performing a correction of the defective bit.
However, by configuring the error correction code to have a high correction capability under any circumstance to increase allowable number of defective cells, decoding process becomes complex, and amount of calculation increases. Accordingly, allowable number of defective cells, that is, the error correcting capability is set based on the importance of the data to be decoded and/or the processing power of the decoder device. Accordingly, in a case where the error correction code is designed to allow two defective cells, errors occurred to three or more bits in the data could not be appropriately corrected.
There is proposed a decoder device that performs an error correction using an erasure correction code. The erasure correction code is for restoring invalid data in the data to be decoded having several bits by using remaining valid data. An example of such decoder device is disclosed in JP-A-2006-236536 (counterpart U.S. publication is: US 2006/0192866 A1). However, the decoder device disclosed in JP-A-2006-236536 has low tolerance for a rapid increase of defective cells (errors).